1. Field of the Invention
The present invention relates to digital memory devices and operation thereof, and more particularly to a NAND flash memory array architecture having low read latency and low program disturb.
2. Description of Related Art
NAND flash memory is popular for data storage. The cost versus density advantage of single level cell (“SLC”) NAND flash memory in densities of 512 Megabits and higher is largely due to the inherently smaller memory cell size used in SLC NAND flash technology.
NAND flash memory is also becoming popular for a variety of applications beyond data storage due to various techniques which have been developed to adapt NAND flash memory to such applications. Unfortunately, NAND flash memory tends to have a lengthy read latency time, which limits the usefulness of NAND flash memory in applications requiring random data access and short sequential and continuous page reads.